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https://www.google.com/imgres?imgurl=http%3A%2F%2Fstorage1.static.itmages.ru%2Fi%2F17%2F1011%2Fs_1507745644_5670027_14116712c3.jpg&imgrefurl=http%3A%2F%2Fforum.easyelectronics.ru%2Fviewtopic.php%3Ff%3D35%26t%3D33197&docid=nvExypM44QncCM&tbnid=DTkWxJAxgaELbM%3A&vet=10ahUKEwiq2JXSkKDkAhV-VBUIHeimBEcQMwg4KAEwAQ..i&w=192&h=176&itg=1&bih=920&biw=1920&q=oki%20m6775t&ved=0ahUKEwiq2JXSkKDkAhV-VBUIHeimBEcQMwg4KAEwAQ&iact=mrc&uact=8

here is the code he eventually come up

/ * Includes ----------------------------------------------- ------------------- * /
#include "stm32f10x.h"
#include "m6775t.h"
#include "m6775t_fonts.h"

uint8_t RAM1_bits0_7, RAM1_bits8_15, RAM1_bits16_23, RAM1_bits24_31 , RAM1_bits32_39, RAM1_bits40_47, RAM1_bits48_55, RAM1_bits56_63, RAM1_bits64_71, RAM1_bits72_79,
RAM2_bits0_7, RAM2_bits8_15, RAM2_bits16_23, RAM2_bits24_31, RAM2_bits32_39, RAM2_bits40_47, RAM2_bits48_55, RAM2_bits56_63, RAM2_bits64_71, RAM2_bits72_79,
RAM3_bits0_7, RAM3_bits8_15, RAM3_bits16_23, RAM3_bits24_31, RAM3_bits32_39, RAM3_bits40_47, RAM3_bits48_55, RAM3_bits56_63, RAM3_bits64_71 , RAM3_bits72_79,
RAM4_bits0_7, RAM4_bits8_15, RAM4_bits16_23, RAM4_bits24_31, RAM4_bits32_39, RAM4_bits40_47, RAM4_bits48_55, RAM4_bits56_63, RAM4_bits64_71, RAM4_bits72_79;

LCD_WRITE void (uint8_t pack0, uint8_t pack1, uint8_t pack2, uint8_t pack3, uint8_t pack4,
uint8_t pack5, uint8_t pack6, uint8_t pack7, uint8_t pack8, uint8_t pack9,
uint8_t latch)
{
SPI1-> DR = pack0;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = pack1;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = pack2;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = pack3;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = pack4;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = pack5;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = pack6;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = pack7;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = pack8;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = pack9;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);

while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = latch;

while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_BSY) == SET);
GPIO_SetBits (GPIOA, SPI_MASTER_NSS);
GPIO_ResetBits (GPIOA, SPI_MASTER_NSS);
}

void CleanLCD (void)
{
SPI1-> DR = 0;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = 0;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = 0;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = 0;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = 0;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = 0;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = 0;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = 0;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = 0;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = 0;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);
SPI1-> DR = 0xff;
while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET);

while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_BSY) == SET);
GPIO_SetBits (GPIOA, SPI_MASTER_NSS);
GPIO_ResetBits (GPIOA, SPI_MASTER_NSS);
}

uint32_t getChar (uint8_t SYMBOL)
{
uint32_t symbol;
if (SYMBOL <32)
{
return 32;
}
else
{
if (SYMBOL> 127) {SYMBOL - = 64;}
SYMBOL - = 32;
symbol = Font_19Seg [SYMBOL];
return (symbol);
}
}

void LCD_WriteText (char string [])
{
uint32_t tempScaler = 0x0;
uint64_t tmpBufRAM1 = 0x0, tmpBufRAM2 = 0x0, tmpBufRAM3 = 0x0, tmpBufRAM4 = 0x0;
// const uint64_t bufferMask = 0x1;

for (uint8_t i = 8; i> 0; i--) // loop for creating the first latch buffer
{
// char SYMBOL = string ;
// Latch string buffer variable
// Buffer filling algorithm // Assign the
first bits to the scaler

tempScaler = getChar (string [i-1]);

// Fill the buffer for the first latch.

tmpBufRAM1 << = 1;
tmpBufRAM2 << = 1;
tmpBufRAM3 << = 1;
tmpBufRAM4 << = 1;
if ((tempScaler >> 14) & 0x1) {tmpBufRAM1 | = 0x1;} else {tmpBufRAM1 & = 0xffffffffffffffff;} // First latch
if ((tempScaler >> 15) & 0x1) {tmpBufRAM2 | = 0x1;} else {tmpBuf = 0xfffffffffffffffffe;} // Second latch
if ((tempScaler >> 17) & 0x1) {tmpBufRAM3 | = 0x1;} else {tmpBufRAM3 & = 0xfffffffffffffffe;} // Third latch
if ((tempScaler >> 18) & 0x1f {tmp = 0x1;} else {tmpBufRAM4 &
tmpBufRAM1 << = 1;
tmpBufRAM2 << = 1;
tmpBufRAM3 << = 1;
tmpBufRAM4 << = 1;
if ((tempScaler >> 9) & 0x1) {tmpBufRAM1 | = 0x1;} else {tmpBufRAM1 & = 0xffffffffffffffff;} // First latch
if ((tempScaler >> 13) & 0x1) {tmpBufRAM2 | = 0x1;} else {tmpBuf = 0xfffffffffffffffffe;} // Second latch
if ((tempScaler >> 12) & 0x1) {tmpBufRAM3 | = 0x1;} else {tmpBufRAM3 & = 0xfffffffffffffffe;} // Third latch
if ((tempScaler >> 16) & 0x1f {tmp = 0x1;} else {tmpBufRAM4 & = 0xfffffffffffffffffe;} // Fourth latch
tmpBufRAM1 << = 1;
tmpBufRAM2 << = 1;
tmpBufRAM3 << = 1;
tmpBufRAM4 << = 1;
if ((tempScaler >> 1) & 0x1) {tmpBufRAM1 | = 0x1;} else {tmpBufRAM1 & = 0xffffffffffffffff;} // First latch
if ((tempScaler >> 11) & 0x1) {tmpBufRAM2 | = 0x1;} else {tmpBuf = 0xfffffffffffffffffe;} // Second latch
if ((tempScaler >> 10) & 0x1) {tmpBufRAM3 | = 0x1;} else {tmpBufRAM3 & = 0xfffffffffffffffe;} // Third latch
if ((tempScaler >> 6) & 0x1f {4mp = 0x1;} else {tmpBufRAM4 & = 0xfffffffffffffffffe;} // Fourth latch
tmpBufRAM1 << = 1;
tmpBufRAM2 << = 1;
tmpBufRAM3 << = 1;
tmpBufRAM4 << = 1;
if ((tempScaler) & 0x1) {tmpBufRAM1 | = 0x1;} else {tmpBufRAM1 & = 0xfffffffffffffffe;} // First latch
if ((tempScaler >> 8) & 0x1) {tmpBufRAM2 | = 0x1;} else {tmpBufRAM2 & = 0xffffffffffffffff;} // Second latch
if ((tempScaler >> 7) & 0x1) {tmpBufRAM3 | = 0x1;} else {tmpBuf = 0xfffffffffffffffffe;} // Third latch
if ((tempScaler >> 5) & 0x1) {tmpBufRAM4 | = 0x1;} else {tmpBufRAM4 & = 0xfffffffffffffffe;} // Fourth latch
tmpBufRAM2 << = 1;
tmpBufRAM3 << = 1;
tmpBufRAM4 << = 1;
if ((tempScaler >> 2) & 0x1) {tmpBufRAM2 | = 0x1;} else {tmpBufRAM2 & = 0xffffffffffffffff;} // Second latch
if ((tempScaler >> 3) & 0x1) {tmpBufRAM3 | = 0x1;} else {tmpBuf = 0xfffffffffffffffffe;} // Third latch
if ((tempScaler >> 4) & 0x1) {tmpBufRAM4 | = 0x1;

// Pull the buffer data into a variable
// First bit
if (tmpBufRAM1 & 0x1) {RAM1_bits16_23 | = 0x04;} else {RAM1_bits16_23 & = 0xfb;} tmpBufRAM1 >> = 1; // 1st latch A
if (tmpBufRAM1 & 0x1) RAM = 0x20;} else {RAM1_bits16_23 & = 0xdf;} tmpBufRAM1 >> = 1; // 1st latch B1
if (tmpBufRAM2 & 0x1) {RAM2_bits16_23 | = 0x20;} else {RAM2_bits16_23 & = 0xdf;} tmpBufRAM2 // 2nd latch B2
if (tmpBufRAM3 & 0x1) {RAM3_bits16_23 | = 0x20;} else {RAM3_bits16_23 & = 0xdf;} tmpBufRAM3 >> = 1; // 3rd latch C1
if (tmpBufRAM4 & 0x1) {RAM4_bits16_ else {RAM4_bits16_23 & = 0xdf;} tmpBufRAM4 >> = 1; // 4th latch C2
if (tmpBufRAM4 & 0x1) {RAM4_bits16_23 | = 0x10;} else {RAM4_bits16_23 & = 0xef;} tmpBufRAM4 >> = 1; // 4th latch D
if (tmpBufRAM4 & 0x1) {RAM4_bits16_23 | = 0x08;} else {RAM4_bits16_23 & = 0xf7;} tmpBufRAM4 >> = 1; // 4th latch E1
if (tmpBufRAM3 & 0x1) {RAM3_bits16_23 | = 0x08; else} } tmpBufRAM3 >> = 1; // 3rd latch E2
if (tmpBufRAM2 & 0x1) {RAM2_bits16_23 | = 0x08;} else {RAM2_bits16_23 & = 0xf7;} tmpBufRAM2 >> = 1; // 2nd latch F1
if (tmpBufR) {RAM1_bits16_23 | = 0x08;} else {RAM1_bits16_23 & = 0xf7;} tmpBufRAM1 >> = 1; // 1st latch F2
if (tmpBufRAM3 & 0x1) {RAM3_bits16_23 | = 0x04;} else {RAM3_bits16_23 & = 0xfffbf} = 1; // 3rd latch G1
if (tmpBufRAM2 & 0x1) {RAM2_bits16_23 | = 0x10;} else {RAM2_bits16_23 & = 0xef;} tmpBufRAM2 >> = 1; // 2nd latch G2
if (tmpBufRAM3 & 0x1) {RAM3_bits16_23 | = 0x02;} else {RAM3_bits16_23 & = 0xfd;} tmpBufRAM3 >> = 1; // 3rd latch G3
if (tmpBufRAM2 & 0x1) {RAM2_bits16_23 | = 0x04; yes } tmpBufRAM2 >> = 1; // 2nd latch H
if (tmpBufRAM1 & 0x1) {RAM1_bits16_23 | = 0x10;} else {RAM1_bits16_23 & = 0xef;} tmpBufRAM1 >> = 1; // 1st latch I
if (tmpBufRAM2 & 0 {RAM2_bits16_23 | = 0x02;} else {RAM2_bits16_23 & = 0xfd;} tmpBufRAM2 >> = 1; // 2nd latch J
if (tmpBufRAM4 & 0x1) {RAM4_bits16_23 | = 0x02;} else {RAM4_bits16_23 & = txffd} = 1; // 4th latch K
if (tmpBufRAM3 & 0x1) {RAM3_bits16_23 | = 0x10;} else {RAM3_bits16_23 & = 0xef;} tmpBufRAM3 >> = 1; // 3rd latch L
if (tmpBufRAM4 & 0x1) {RAM4_bits16_23 | = 0x04;} else {RAM4_bits16_23 & = 0xfb;} tmpBufRAM4 >> = 1; // 4th latch M
// Second digit
/ *
<< 7 - 0x80 - inverse - 0x7f
<< 6 - 0x40 - inverse - 0xbf
<< 5 - 0x20 - inverse - 0xdf
<< 4 - 0x10 - inverse - 0xef
<< 3 - 0x08 - inverse - 0xf7
<< 2 - 0x04 - inverse - 0xfb
<< 1 - 0x02 - inverse - 0xfd
<< 0 - 0x01 - inverse - 0xfe
* /
if (tmpBufRAM1 & 0x1) {RAM1_bits16_23 | = 0x80;} else {RAM1_bits16_23 & = 0x7f;} tmpBufRAM1 >> = 1; // 1st latch A
if (tmpBufR31_311 0 & 1 | = 0x02;} else {RAM1_bits24_31 & = 0xfd;} tmpBufRAM1 >> = 1; // 1st latch B1
if (tmpBufRAM2 & 0x1) {RAM2_bits24_31 | = 0x02;} else {RAM2_bits24_31 & = 0xfd;} tmpBufRAM2 >> = 1; // 2nd latch B2
if (tmpBufRAM3 & 0x1) {RAM3_bits24_31 | = 0x3;} } tmpBufRAM3 >> = 1; // 3rd latch C1
if (tmpBufRAM4 & 0x1) {RAM4_bits24_31 | = 0x02;} else {RAM4_bits24_31 & = 0xfd;} tmpBufRAM4 >> = 1; // 4th latch C2
if (tmpBuf) {RAM4_bits24_31 | = 0x01;} else {RAM4_bits24_31 & = 0xfe;} tmpBufRAM4 >> = 1; // 4th latch D
if (tmpBufRAM4 & 0x1) {RAM4_bits16_23 | = 0x40;} else {RAM4_bits16_23 & = 0xbf; = 1; // 4th latch E1
if (tmpBufRAM3 & 0x1) {RAM3_bits16_23 | = 0x40;} else {RAM3_bits16_23 & = 0xbf;} tmpBufRAM3 >> = 1; // 3rd latch E2
if (tmpBufRAM2 & 0x1) {RAM2_bits16_23 | = 0x40;} else {RAM2_bits16_23 & = 0xbf;} tmpBufRAM2 >> = 1; // 2nd latch F1
if (tmpBufRAM1 & 0x1) {RAM1_bits16_23 | = 0x40;} else } tmpBufRAM1 >> = 1; // 1st latch F2
if (tmpBufRAM3 & 0x1) {RAM3_bits16_23 | = 0x80;} else {RAM3_bits16_23 & = 0x7f;} tmpBufRAM3 >> = 1; // 3rd latch G1
if (tmpBuf) {RAM2_bits24_31 | = 0x01;} else {RAM2_bits24_31 & = 0xfe;} tmpBufRAM2 >> = 1; // 2nd latch G2
if (tmpBufRAM3 & 0x1) {RAM3_bits16_23 | = 0x01;} else {RAM3_bits16_23 & = 0xfe; = 1; // 3rd latch G3
if (tmpBufRAM2 & 0x1) {RAM2_bits16_23 | = 0x80;} else {RAM2_bits16_23 & = 0x7f;} tmpBufRAM2 >> = 1; // 2nd latch H
if (tmpBufRAM1 & 0x1) {RAM1_bits24_31 | = 0x01;} else {RAM1_bits24_31 & = 0xfe;} tmpBufRAM1 >> = 1; // 1st latch I
if (tmpBufRAM2 & 0x1) {RAM2_bits16_23 | = 0x01 ;fe {0x01;} } tmpBufRAM2 >> = 1; // 2nd latch J
if (tmpBufRAM4 & 0x1) {RAM4_bits16_23 | = 0x01;} else {RAM4_bits16_23 & = 0xfe;} tmpBufRAM4 >> = 1; // 4th latch K
if (tmpBuxRAM3 & 0 {RAM3_bits24_31 | = 0x01;} else {RAM3_bits24_31 & = 0xfe;} tmpBufRAM3 >> = 1; // 3rd latch L
if (tmpBufRAM4 & 0x1) {RAM4_bits16_23 | = 0x80;} else {RAM4_bits16_23 & = 0x7f; = 1; // 4th latch M
// Third digit
if (tmpBufRAM1 & 0x1) {RAM1_bits24_31 | = 0x08;} else {RAM1_bits24_31 & = 0xf7;} tmpBufRAM1 >> = 1; // 1st latch A
if (tmpBufRAM1 & 0x1) {RAM1_bits48_55 | = 0x02;} else {RAM1_bits48_55 & = 0xfd;} tmpBufRAM1 >> = 1; // 1st latch B1
if (tmpBufRAM2 & 0x1) {RAM2_bits48_55 | = 0x2;} } tmpBufRAM2 >> = 1; // 2nd latch B2
if (tmpBufRAM3 & 0x1) {RAM3_bits48_55 | = 0x02;} else {RAM3_bits48_55 & = 0xfd;} tmpBufRAM3 >> = 1; // 3rd latch C1
if (tmpBufR) {RAM4_bits48_55 | = 0x02;} else {RAM4_bits48_55 & = 0xfd;} tmpBufRAM4 >> = 1; // 4th latch C2
if (tmpBufRAM4 & 0x1) {RAM4_bits48_55 | = 0x01;} else {RAM4_bits48_55 & = 0xfe | = 1; // 4th latch D
if (tmpBufRAM4 & 0x1) {RAM4_bits24_31 | = 0x04;} else {RAM4_bits24_31 & = 0xfb;} tmpBufRAM4 >> = 1; // 4th latch E1
if (tmpBufRAM3 & 0x1) {RAM3_bits24_31 | = 0x04;} else {RAM3_bits24_31 & = 0xfb;} tmpBufRAM3 >> = 1; // 3rd latch E2
if (tmpBufRAM2 & 0x1) {RAM2_bits24_31 | = 0x04; yes } tmpBufRAM2 >> = 1; // 2nd latch F1
if (tmpBufRAM1 & 0x1) {RAM1_bits24_31 | = 0x04;} else {RAM1_bits24_31 & = 0xfb;} tmpBufRAM1 >> = 1; // 1st latch F2
if (tmpBufR) {RAM3_bits24_31 | = 0x08;} else {RAM3_bits24_31 & = 0xf7;} tmpBufRAM3 >> = 1; // 3rd latch G1
if (tmpBufRAM2 & 0x1) {RAM2_bits48_55 | = 0x01;} else {RAM2_bits48_55 & = 0xfe | = 1; // 2nd latch G2
if (tmpBufRAM3 & 0x1) {RAM3_bits8_15 | = 0x80;} else {RAM3_bits8_15 & = 0x7f;} tmpBufRAM3 >> = 1; // 3rd latch G3
if (tmpBufRAM2 & 0x1) {RAM2_bits24_31 | = 0x08;} else {RAM2_bits24_31 & = 0xf7;} tmpBufRAM2 >> = 1; // 2nd latch H
if (tmpBufRAM1 & 0x1) {RAM1_bits48_55 | = 0x01;} } tmpBufRAM1 >> = 1; // 1st latch I
if (tmpBufRAM2 & 0x1) {RAM2_bits8_15 | = 0x80;} else {RAM2_bits8_15 & = 0x7f;} tmpBufRAM2 >> = 1; // 2nd latch J
if (tmpBuxR4) {RAM4_bits8_15 | = 0x80;} else {RAM4_bits8_15 & = 0x7f;} tmpBufRAM4 >> = 1; // 4th latch K
if (tmpBufRAM3 & 0x1) {RAM3_bits48_55 | = 0x01;} else {RAM3_bits48_55 & = 0xfe; = 1; // 3rd latch L
if (tmpBufRAM4 & 0x1) {RAM4_bits24_31 | = 0x08;} else {RAM4_bits24_31 & = 0xf7;} tmpBufRAM4 >> = 1; // 4th latch M
// Fourth digit
if (tmpBufRAM1 & 0x1) {RAM1_bits48_55 | = 0x08;} else {RAM1_bits48_55 & = 0xf7;} tmpBufRAM1 >> = 1; // 1st latch A
if (tmpBufRAM1 & 0x1) {RAM1_bits48_55 | = 0x1; = 0x40;} } tmpBufRAM1 >> = 1; // 1st latch B1
if (tmpBufRAM2 & 0x1) {RAM2_bits48_55 | = 0x40;} else {RAM2_bits48_55 & = 0xbf;} tmpBufRAM2 >> = 1; // 2nd latch B2
if (tmpBu1R) {RAM3_bits48_55 | = 0x40;} else {RAM3_bits48_55 & = 0xbf;} tmpBufRAM3 >> = 1; // 3rd latch C1
if (tmpBufRAM4 & 0x1) {RAM4_bits48_55 | = 0x40;} else {RAM4_bits48_55 & = 0xffRf} = 1; // 4th latch C2
if (tmpBufRAM4 & 0x1) {RAM4_bits48_55 | = 0x10;} else {RAM4_bits48_55 & = 0xef;} tmpBufRAM4 >> = 1; // 4th latch D
if (tmpBufRAM4 & 0x1) {RAM4_bits48_55 | = 0x04;} else {RAM4_bits48_55 & = 0xfb;} tmpBufRAM4 >> = 1; // 4th latch E1
if (tmpBufRAM3 & 0x1) {RAM3_bits48_55 | = 0x04; yes = 0x04; } tmpBufRAM3 >> = 1; // 3rd latch E2
if (tmpBufRAM2 & 0x1) {RAM2_bits48_55 | = 0x04;} else {RAM2_bits48_55 & = 0xfb;} tmpBufRAM2 >> = 1; // 2nd latch F1
if (tmpBufR) {RAM1_bits48_55 | = 0x04;} else {RAM1_bits48_55 & = 0xfb;} tmpBufRAM1 >> = 1; // 1st latch F2
if (tmpBufRAM3 & 0x1) {RAM3_bits48_55 | = 0x08;} else {RAM3_bits48_55 & = 0xffRf3f3f3f3frfff7f} = 1; // 3rd latch G1
if (tmpBufRAM2 & 0x1) {RAM2_bits48_55 | = 0x10;} else {RAM2_bits48_55 & = 0xef;} tmpBufRAM2 >> = 1; // 2nd latch G2
if (tmpBufRAM3 & 0x1) {RAM3_bits48_55 | = 0x20;} else {RAM3_bits48_55 & = 0xdf;} tmpBufRAM3 >> = 1; // 3rd latch G3
if (tmpBufRAM2 & 0x1) {RAM2_bits48_55 | = 0x08;} } tmpBufRAM2 >> = 1; // 2nd latch H
if (tmpBufRAM1 & 0x1) {RAM1_bits48_55 | = 0x10;} else {RAM1_bits48_55 & = 0xef;} tmpBufRAM1 >> = 1; // 1st latch I
if (tmpBufRAM2 & 0 {RAM2_bits48_55 | = 0x20;} else {RAM2_bits48_55 & = 0xdf;} tmpBufRAM2 >> = 1; // 2nd latch J
if (tmpBufRAM4 & 0x1) {RAM4_bits48_55 | = 0x20;} else {RAM4_bits48_55 & = 0xdf; = 1; // 4th latch K
if (tmpBufRAM3 & 0x1) {RAM3_bits48_55 | = 0x10;} else {RAM3_bits48_55 & = 0xef;} tmpBufRAM3 >> = 1; // 3rd latch L
if (tmpBufRAM4 & 0x1) {RAM4_bits48_55 | = 0x08;} else {RAM4_bits48_55 & = 0xf7;} tmpBufRAM4 >> = 1; // 4th latch M
// Fifth bit
if (tmpBufRAM1 & 0x1) {RAM1_bits56_63_63 else = & = 0xdf;} tmpBufRAM1 >> = 1; // 1st latch A
if (tmpBufRAM1 & 0x1) {RAM1_bits64_71 | = 0x01;} else {RAM1_bits64_71 & = 0xfe;} tmpBufRAM1 >> = 1; // 1st latch B1
if (tmpBufRAM2 & 0x1) {RAM2_bits64_71 | = 0x01;} else {RAM2_bits64_71 & = 0xfe;} tmpBufRAM2 >> = 1; // 2nd latch B2
if (tmpBufRAM3 & 0x1) {RAM3_bits64_71 | = 0x01 ;fe {1x3; } tmpBufRAM3 >> = 1; // 3rd latch C1
if (tmpBufRAM4 & 0x1) {RAM4_bits64_71 | = 0x01;} else {RAM4_bits64_71 & = 0xfe;} tmpBufRAM4 >> = 1; // 4th latch C2
if (tmpBufRAM4 & 0x1) {RAM4_bits56_63 | = 0x40;} else {RAM4_bits56_63 & = 0xbf;} tmpBufRAM4 >> = 1; // 4th latch D
if (tmpBufRAM4 & 0x1) {RAM4_bits56_63 | = 0x10;} else } tmpBufRAM4 >> = 1; // 4th latch E1
if (tmpBufRAM3 & 0x1) {RAM3_bits56_63 | = 0x10;} else {RAM3_bits56_63 & = 0xef;} tmpBufRAM3 >> = 1; // 3rd latch E2
if (tmpBuxR2) {RAM2_bits56_63 | = 0x10;} else {RAM2_bits56_63 & = 0xef;} tmpBufRAM2 >> = 1; // 2nd latch F1
if (tmpBufRAM1 & 0x1) {RAM1_bits56_63 | = 0x10;} else {RAM1_bits56_63 & = 0xef;} tmp = 1; // 1st latch F2
if (tmpBufRAM3 & 0x1) {RAM3_bits56_63 | = 0x20;} else {RAM3_bits56_63 & = 0xdf;} tmpBufRAM3 >> = 1; // 3rd latch G1
if (tmpBufRAM2 & 0x1) {RAM2_bits56_63 | = 0x40;} else {RAM2_bits56_63 & = 0xbf;} tmpBufRAM2 >> = 1; // 2nd latch G2
if (tmpBufRAM3 & 0x1) {RAM3_bits56_63 | = 0x80; else} } tmpBufRAM3 >> = 1; // 3rd latch G3
if (tmpBufRAM2 & 0x1) {RAM2_bits56_63 | = 0x20;} else {RAM2_bits56_63 & = 0xdf;} tmpBufRAM2 >> = 1; // 2nd latch H
if (tmpBuxR1) {RAM1_bits56_63 | = 0x40;} else {RAM1_bits56_63 & = 0xbf;} tmpBufRAM1 >> = 1; // 1st latch I
if (tmpBufRAM2 & 0x1) {RAM2_bits56_63 | = 0x80;} else {RAM2_bits56_63 & = 0x7f; = 1; // 2nd latch J
if (tmpBufRAM4 & 0x1) {RAM4_bits56_63 | = 0x80;} else {RAM4_bits56_63 & = 0x7f;} tmpBufRAM4 >> = 1; // 4th latch K
if (tmpBufRAM3 & 0x1) {RAM3_bits56_63 | = 0x40;} else {RAM3_bits56_63 & = 0xbf;} tmpBufRAM3 >> = 1; // 3rd latch L
if (tmpBufRAM4 & 0x1) {RAM4_bits56_63 | = 0x20; }df } tmpBufRAM4 >> = 1; // 4th latch M
// Sixth digit
if (tmpBufRAM1 & 0x1) {RAM1_bits64_71 | = 0x04;} else {RAM1_bits64_71 & = 0xfb;} tmpBufRAM1 >> = 1; // 1st latch A
if (tmpBufRAM1 & 0x1) {RAM1_bits64_71 | = 0x20;} else {RAM1_bits64_71 & = 0xdf;} tmpBufRAM1 >> = 1; // 1st latch B1
if (tmpBufRAM2 & 0x1) {RAM2_bits64_71 | = 0x20;} } tmpBufRAM2 >> = 1; // 2nd latch B2
if (tmpBufRAM3 & 0x1) {RAM3_bits64_71 | = 0x20;} else {RAM3_bits64_71 & = 0xdf;} tmpBufRAM3 >> = 1; // 3rd latch C1
if (tmpBufRAM4 & 0x1) {RAM4_bits64_71 | = 0x20;} else {RAM4_bits64_71 & = 0xdf;} tmpBufRAM4 >> = 1; // 4th latch C2
if (tmpBufRAM4 & 0x1) {RAM4_bits64_71 | = 0x08;} } tmpBufRAM4 >> = 1; // 4th latch D
if (tmpBufRAM4 & 0x1) {RAM4_bits64_71 | = 0x02;} else {RAM4_bits64_71 & = 0xfd;} tmpBufRAM4 >> = 1; // 4th latch E1
if (tmpBufR) {RAM3_bits64_71 | = 0x02;} else {RAM3_bits64_71 & = 0xfd;} tmpBufRAM3 >> = 1; // 3rd latch E2
if (tmpBufRAM2 & 0x1) {RAM2_bits64_71 | = 0x02;} else {RAM2_bits64_71 & = 2xf >> = 1; // 2nd latch F1
if (tmpBufRAM1 & 0x1) {RAM1_bits64_71 | = 0x02;} else {RAM1_bits64_71 & = 0xfd;} tmpBufRAM1 >> = 1; // 1st latch F2
if (tmpBufRAM3 & 0x1) {RAM3_bits64_71 | = 0x04;} else {RAM3_bits64_71 & = 0xfb;} tmpBufRAM3 >> = 1; // 3rd latch G1
if (tmpBufRAM2 & 0x1) {RAM2_bits64_71 | = 0x0; 2 = 0x08; } tmpBufRAM2 >> = 1; // 2nd latch G2
if (tmpBufRAM3 & 0x1) {RAM3_bits64_71 | = 0x10;} else {RAM3_bits64_71 & = 0xef;} tmpBufRAM3 >> = 1; // 3rd latch G3
if (tmpBuxR2) {RAM2_bits64_71 | = 0x04;} else {RAM2_bits64_71 & = 0xfb;} tmpBufRAM2 >> = 1; // 2nd latch H
if (tmpBufRAM1 & 0x1) {RAM1_bits64_71 | = 0x08;} else {RAM1_bits64_71 & = 0xf7; = 1; // 1st latch I
if (tmpBufRAM2 & 0x1) {RAM2_bits64_71 | = 0x10;} else {RAM2_bits64_71 & = 0xef;} tmpBufRAM2 >> = 1; // 2nd latch J
if (tmpBufRAM4 & 0x1) {RAM4_bits64_71 | = 0x10;} else {RAM4_bits64_71 & = 0xef;} tmpBufRAM4 >> = 1; // 4th latch K
if (tmpBufRAM3 & 0x1) {RAM3_bits64_71 | = 0x08; _7 {{ } tmpBufRAM3 >> = 1; // 3rd latch L
if (tmpBufRAM4 & 0x1) {RAM4_bits64_71 | = 0x04;} else {RAM4_bits64_71 & = 0xfb;} tmpBufRAM4 >> = 1; // 4th latch M
// Seventh digit
if (tmpBufRAM1 & 0x1) {RAM1_bits64_71 | = 0x80;} else {RAM1_bits64_71 & = 0x7f;} tmpBufRAM1 >> = 1; // 1st latch A
if (tmpBufRAM1 & 0x1) {RAM1_bits72_79 | = 0x04;} =} } tmpBufRAM1 >> = 1; // 1st latch B1
if (tmpBufRAM2 & 0x1) {RAM2_bits72_79 | = 0x04;} else {RAM2_bits72_79 & = 0xfb;} tmpBufRAM2 >> = 1; // 2nd latch B2
if (tmpBufRAM3 & 0x1) {RAM3_bits72_79 | = 0x04;} else {RAM3_bits72_79 & = 0xfb;} tmpBufRAM3 >> = 1; // 3rd latch C1
if (tmpBufRAM4 & 0x1) {RAM4_bits72_79 | = 0x04; else = 0x04; } tmpBufRAM4 >> = 1; // 4th latch C2
if (tmpBufRAM4 & 0x1) {RAM4_bits72_79 | = 0x01;} else {RAM4_bits72_79 & = 0xfe;} tmpBufRAM4 >> = 1; // 4th latch D
if (tmpBuxR4) {RAM4_bits64_71 | = 0x40;} else {RAM4_bits64_71 & = 0xbf;} tmpBufRAM4 >> = 1; // 4th latch E1
if (tmpBufRAM3 & 0x1) {RAM3_bits64_71 | = 0x40;} else {RAM3_bits64_71 & = 0xbf = 1; // 3rd latch E2
if (tmpBufRAM2 & 0x1) {RAM2_bits64_71 | = 0x40;} else {RAM2_bits64_71 & = 0xbf;} tmpBufRAM2 >> = 1; // 2nd latch F1
if (tmpBufRAM1 & 0x1) {RAM1_bits64_71 | = 0x40;} else {RAM1_bits64_71 & = 0xbf;} tmpBufRAM1 >> = 1; // 1st latch F2
if (tmpBufRAM3 & 0x1) {RAM3_bits64_71 | = 0x80; else} } tmpBufRAM3 >> = 1; // 3rd latch G1
if (tmpBufRAM2 & 0x1) {RAM2_bits72_79 | = 0x01;} else {RAM2_bits72_79 & = 0xfe;} tmpBufRAM2 >> = 1; // 2nd latch G2
if (tmpBufR) {RAM3_bits72_79 | = 0x02;} else {RAM3_bits72_79 & = 0xfd;} tmpBufRAM3 >> = 1; // 3rd latch G3
if (tmpBufRAM2 & 0x1) {RAM2_bits64_71 | = 0x80;} else {RAM2_bits64_71 & = 0xf} = 1; // 2nd latch H
if (tmpBufRAM1 & 0x1) {RAM1_bits72_79 | = 0x01;} else {RAM1_bits72_79 & = 0xfe;} tmpBufRAM1 >> = 1; // 1st latch I
if (tmpBufRAM2 & 0x1) {RAM2_bits72_79 | = 0x02;} else {RAM2_bits72_79 & = 0xfd;} tmpBufRAM2 >> = 1; // 2nd latch J
if (tmpBufRAM4 & 0x1) {RAM4_bits72_79 | = 0x4; else} } tmpBufRAM4 >> = 1; // 4th latch K
if (tmpBufRAM3 & 0x1) {RAM3_bits72_79 | = 0x01;} else {RAM3_bits72_79 & = 0xfe;} tmpBufRAM3 >> = 1; // 3rd latch L
if (tmpBuxRAM4 & 0 {RAM4_bits64_71 | = 0x80;} else {RAM4_bits64_71 & = 0x7f;} tmpBufRAM4 >> = 1; // 4th latch M
// Eighth bit
if (tmpBufRAM1 & 0x1) {RAM1_bits72_79 | = 0x10;} else {RAM1_bits72_79 & = = } tmpBufRAM1 >> = 1; // 1st latch A
if (tmpBufRAM1 & 0x1) {RAM1_bits72_79 | = 0x80;} else {RAM1_bits72_79 & = 0x7f;} tmpBufRAM1 >> = 1; // 1st latch B1
if (tmpBufRAM2 & 0x1) {RAM2_bits72_79 | = 0x80;} else {RAM2_bits72_79 & = 0x7f;} tmpBufRAM2 >> = 1; // 2nd latch B2
if (tmpBufRAM3 & 0x1) {RAM3_bits72_79 | = 0x80;} else } tmpBufRAM3 >> = 1; // 3rd latch C1
if (tmpBufRAM4 & 0x1) {RAM4_bits72_79 | = 0x80;} else {RAM4_bits72_79 & = 0x7f;} tmpBufRAM4 >> = 1; // 4th latch C2
if (tmpBuf) {RAM4_bits72_79 | = 0x20;} else {RAM4_bits72_79 & = 0xdf;} tmpBufRAM4 >> = 1; // 4th latch D
if (tmpBufRAM4 & 0x1) {RAM4_bits72_79 | = 0x08;} else {RAM4_bits72_79 & = 0xff;} = 1; // 4th latch E1
if (tmpBufRAM3 & 0x1) {RAM3_bits72_79 | = 0x08;} else {RAM3_bits72_79 & = 0xf7;} tmpBufRAM3 >> = 1; // 3rd latch E2
if (tmpBufRAM2 & 0x1) {RAM2_bits72_79 | = 0x08;} else {RAM2_bits72_79 & = 0xf7;} tmpBufRAM2 >> = 1; // 2nd latch F1
if (tmpBufRAM1 & 0x1) {RAM1_bits72_79 | = 0x08;} else } tmpBufRAM1 >> = 1; // 1st latch F2
if (tmpBufRAM3 & 0x1) {RAM3_bits72_79 | = 0x10;} else {RAM3_bits72_79 & = 0xef;} tmpBufRAM3 >> = 1; // 3rd latch G1
if (tmpBuxR2) {RAM2_bits72_79 | = 0x20;} else {RAM2_bits72_79 & = 0xdf;} tmpBufRAM2 >> = 1; // 2nd latch G2
if (tmpBufRAM3 & 0x1) {RAM3_bits72_79 | = 0x40;} else {RAM3_bits72_79 & = 0xbf; = 1; // 3rd latch G3
if (tmpBufRAM2 & 0x1) {RAM2_bits72_79 | = 0x10;} else {RAM2_bits72_79 & = 0xef;} tmpBufRAM2 >> = 1; // 2nd latch H
if (tmpBufRAM1 & 0x1) {RAM1_bits72_79 | = 0x20;} else {RAM1_bits72_79 & = 0xdf;} tmpBufRAM1 >> = 1; // 1st latch I
if (tmpBufRAM2 & 0x1) {RAM2_bits72_79 | = 0x40;} {RAM2_bits72_79 | = 0x40;} } tmpBufRAM2 >> = 1; // 2nd latch J
if (tmpBufRAM4 & 0x1) {RAM4_bits72_79 | = 0x40;} else {RAM4_bits72_79 & = 0xbf;} tmpBufRAM4 >> = 1; // 4th latch K
if (tmpBuxR3) {RAM3_bits72_79 | = 0x20;} else {RAM3_bits72_79 & = 0xdf;} tmpBufRAM3 >> = 1; // 3rd latch L
if (tmpBufRAM4 & 0x1) {RAM4_bits72_79 | = 0x10;} else {RAM4_bits72_79 & = 0xef;} tmpB} = 1; // 4th latch M
}


how can we apply this in our our patch modules , that is far beyond my knowledge
 

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just brain storming;

how about a small universal lcd display fits in and shows whatever it gets

I happened to see some development kits (board and display)
 

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or even better this one:

https://www.ebay.com/itm/New-2-4-inch-Nextion-HMI-TFT-LCD-Display-Module-For-Arduino-Raspberry-Pi-SK1-/173019921254

we just need someone to set this screen to show car data coming from patch modules(connects2) in a grapical interface
(this seems easier than remapping the stock sub screen, and also stock sub screen has lack of segments like date, fan speed etc.)

once it is done, setup file will be shared, so anyone having the lcd kit can apply this to his car


https://www.civinfo.com/wiki/index.php/File:No_audio.jpg

I assume cavity (1 and 10) is where to look for
 

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I just tested part of the infotainment system I will be installing on my Civic. It consists of a Honda navigation display driven by a universal RGB interface by Car Solutions, a Pioneer ND-BC20PA reverse camera and a 2DIN Android Auto head unit. I am still researching on the choice of the head unit - it will probably be a Sony XAV-AX200 or a Pioneer SPH-DA230DAB. The nice thing about the RGB interface is that it drives the Honda display very well and allows the connection of 2 more composite inputs, so the plan is to link the head unit output to it. Once I have everything, I will do the installation and post more photos.
What connections have you made to turn on the screen and watch the video?
Thanks
 

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It took me a whole day, but I managed to map the pins of the nav sub-display. A total of 4 X 60 = 240 combinations of pins activating a different segment of the display. Now I need to do the same to the non-nav sub-display and see if I can rewire the nav one according to the non-nav. If I am lucky, it will be possible and then I will be able to connect the nav sub-display to the connects2 harness.
ioannis please check out my thread, I would be grateful if you can help me in this project

https://www.civinfo.com/forum/electronics-8g/423040-custom-made-hvac-sub-audio-display.html
 

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What connections have you made to turn on the screen and watch the video?
Thanks


to power up the display, you need:
1) rgb signals (red, blue, green and sync) coming from a rgb video source (Pins 8-9-18-19)
2) ground for rgb signals (Pin 17)
3) continious power (12 volts ) (Pin 1)
4) ignition power (VCC 12 volts) (Pin 2)
5) ground for the display itself (Pin 10)
 

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to power up the display, you need:
1) rgb signals (red, blue, green and sync) coming from a rgb video source (Pins 8-9-18-19)
2) ground for rgb signals (Pin 17)
3) continious power (12 volts ) (Pin 1)
4) ignition power (VCC 12 volts) (Pin 2)
5) ground for the display itself (Pin 10)
thanks man, but one question:

How do I connect my RCA rear camera (yellow connector) to the screen, I think, the screen format is RGB?
Do I have to buy a separator or something similar?
Thank you
 

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Discussion Starter #32
What connections have you made to turn on the screen and watch the video?
Thanks
I am very sorry for taking this long to respond. I haven't been visiting the forum for some time. I will try to provide more information.
 

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Discussion Starter #33
thanks man, but one question:

How do I connect my RCA rear camera (yellow connector) to the screen, I think, the screen format is RGB?
Do I have to buy a separator or something similar?
Thank you
I used the RGB interface to convert the composite signal (RCA connection) to RGB signals that can drive the Honda colour LCD screen.
 

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Discussion Starter #34
ioannis please check out my thread, I would be grateful if you can help me in this project

AC/Heater - Custom Made Hvac Sub Audio Display
I am starting to follow things after all this time I wasn't visiting the forum. Your thread seems interesting. I thought the whole project was a dead end but now I will start looking at it again. I still have all the hardware waiting...
 

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thanks man, but one question:

How do I connect my RCA rear camera (yellow connector) to the screen, I think, the screen format is RGB?
Do I have to buy a separator or something similar?
Thank you
sorry I am late to answer

like ioannis said, you should use a rca to rgb converter I think
 

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I am starting to follow things after all this time I wasn't visiting the forum. Your thread seems interesting. I thought the whole project was a dead end but now I will start looking at it again. I still have all the hardware waiting...
I have contacted a russian friend who managed to read climate data using an arduino, I am very close to success.
I will share everything here when I am fully satisfied
 

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I just tested part of the infotainment system I will be installing on my Civic. It consists of a Honda navigation display driven by a universal RGB interface by Car Solutions, a Pioneer ND-BC20PA reverse camera and a 2DIN Android Auto head unit. I am still researching on the choice of the head unit - it will probably be a Sony XAV-AX200 or a Pioneer SPH-DA230DAB. The nice thing about the RGB interface is that it drives the Honda display very well and allows the connection of 2 more composite inputs, so the plan is to link the head unit output to it. Once I have everything, I will do the installation and post more photos.





Hey I saw your post and I'm new to this, I bought a 2009 civic with navigation but I'll be exporting to the Caribbean where I live,thing is I wanted to install a rear camera to the nav system cause I dont think it will work over here and it's a small island anyway.so my question is will this work for me cause I think the post 09 models are different or some thing like this ....please any help will be appreciated cause I'll be exporting month end
 

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this is such a cool
project!!!!!
i managed to instal the oem navigation unit on my non navi civic si.
i’ll watch this closely as i was wondering how to /if to upgrade.
link to the instal here:


i love the look of the factory display and cd/navi unit. I bought the car based on it’s interior and exterior design .

the thought of the double din radios and blanking that perfectly placed display sickens me:)
 
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